Serial data links are used for communication between a transmitter and a receiver. Systems using serial data links often include serializer-deserializers (SerDes, or SERDES), which consist of a pair of functional blocks, one at each of the transmitter and receiver, that are used for high-speed communication between two nodes, such as two application-specific integrated circuits (ASICs), across a limited input/output link between the two nodes.
Some nodes will include at least one transmitter and at least one receiver, thereby allowing bidirectional communication, although some such communication systems will use only transmitters on the first node and only receivers on the second node. In any case, serial data links are traditionally designed with standalone transmitter (TX) and receiver (RX) sides.
For a serial data link to operate most efficiently, it is desirable for the TX and RX ends of the link to be able to share performance-related information. However, most systems do not have an inherent ability to communicate this information between the transmitter and receiver or vice-versa. Serial data links communicate high-speed data from node to node (e.g. ASIC to ASIC), but are not able to add overhead data to live bit streams, so the performance-related information cannot be encoded in the data stream. Therefore, it is not possible to communicate performance-related information over a serial data link when the data link is active.
One known solution to this problem is to use dedicated circuitry, pins and physical wire connections to create a dedicated physical backchannel for communication of performance-related information or other metadata from the receiver back towards the transmitter of the serial connection. However, this is a large, undesirable overhead because the number of pins available is tightly constrained. A block diagram of an example implementation of such a physical backchannel is shown in FIG. 1. A serial transmission system makes use of a SerDes 100. The SerDes 100 is a Serializer 106 at the transmitter, and a DeSerializer 108 at the receiver. The Serializer 106 and Deserializer 108 form a portion of each of a first application-specific integrated circuit (ASIC) 102 and a second ASIC 104 respectively. The SerDes 100 can be implemented a transmitter macro 106 and a receiver macro 108. Those skilled in the art will appreciate that in an ASIC, the term macro may refer to a somewhat predefined physical design providing a set of functions, the macro design can be used in the implementation of any of the number of different ASIC designs. A data channel 110 allows the transmitter 106 to transmit data to the receiver 108. Physical backchannels 112 are created using physical hardware, such as pins and wires of a data connection. These backchannels 112 may be unidirectional or bidirectional, depending on the physical hardware set aside for them.
The data link may also be used to communicate performance information or other metadata, but not during operation. Existing standards and implementations use existing channels to pass data between chips at startup time as part of a hand-shaking procedure. This hand-shaking usually consists of two parts: auto negotiation (AN) and link training (LT). Auto negotiation is used mainly to configure both sides (TX and RX) to use the same standard, duplex mode and data rate. Link training is used mainly to configure TX amplitudes and equalizer settings. This communication typically happens at lower speed and requires that high speed pseudo-random bit sequence (PRBS) be transmitted periodically so that clock and data recovery (CDR) remains phase-locked.
Because this all occurs only at start up, it cannot respond to any changes in conditions during operation. Link parameters must therefore be set pessimistically, which hurts efficiency. This also affects the speed at which links can be turned on, which further hurts efficiency.
Some techniques have been developed to embed analog back-channel communication on existing data lines.
For example, changing the common mode level of the differential TX or RX circuits may allow some metadata to be embedded in the data signal while the link is operational. One such technique is disclosed by A. Ho, et al., “Common-Mode Backchannel Signaling System for Differential High-Speed Links”, IEEE Symp. VLSI Circuits, June 2004.
However, it is difficult for this kind of modulation technique to have no impact on the signal integrity of the data, especially at very high data rates. It also requires a differential (two-wire) electrical physical link—it is not suitable for optical links or single-ended (one-wire) electrical links.
Another similar modulation technique is disclosed by P. Ta, et al., “Using Frequency Divisional Multiplexing for a high-Speed Serializer/Deserializer with Back Channel Communication”, U.S. Patent Application Number 20110038386, Published Feb. 17, 2011. SerDes links are sometimes alternating current (AC) coupled—where they are, the low-frequency part of the spectrum may be used for back-channel communication.
FIG. 2 shows an example implementation of such a technique from that publication. A circuit 300 is shown having a first SerDes 302 and second SerDes 304. The first SerDes 302 has a forward channel driver 306 as well as a receiver 308 for reverse channel communication; the second SerDes 304 has a reverse channel driver 310 and a receiver 312 for forward channel communication. Two AC coupling capacitors 314,315 enable the circuit to utilize frequency division multiplexing, which enables bi-directional transmission across a communications medium 316. The forward channel passes relatively high frequency signals output by the forward channel driver 306 through a first AC coupling capacitor 314, which are transmitted through the communications medium 316 and passed through a second AC coupling capacitor 315 to be received by the forward channel receiver 312. On the reverse channel 318, the reverse channel driver 310 passes relatively low frequency signals, which bypass the second AC coupling capacitor 315 through DC coupling, are transmitted through the communications medium 316, bypass the first AC coupling capacitor 314, and are received by the reverse channel receiver 308 through DC coupling.
However, this technique is not applicable to links that are not AC coupled. It requires additional pins and external capacitors in order to set the low-frequency cutoff correctly. It also adds complexity to the analog data path, which may introduce noise or other non-idealities. As with the common mode modulation technique disclosed by Ho et al., it requires an electrical physical link and so is not suitable for optical links.